1. Field of the Invention
The present invention relates in general to a stress test apparatus and method for a semiconductor memory device, and more particularly to a stress test apparatus and method in which a cell plate voltage of a dynamic random access memory (referred to hereinafter as DRAM) is applied and varied to stress storage capacitors at the same time and within a short time.
2. Description of the Prior Art
Generally, a stress test operation is for previously removing a chip with a potential fault to prevent an error from occurring when a semiconductor memory device is in use.
In a conventional storage capacitor stressing method, a stress test operation is enabled by fixing a cell plate voltage to half a supply voltage (referred to hereinafter as "half voltage") Vcc/2 and driving a word line. In more detail, in a standby mode, a bit line is precharged with the half voltage Vcc/2, a supply voltage Vcc or a ground voltage Gnd is stored at a storage node, and the half voltage Vcc/2 is applied to a cell plate terminal. If the word line is driven under the above condition, a voltage Vcc/2+.DELTA.V or Vcc/2-.DELTA.V is generated on the bit line and storage node by the charge distribution through a turned-on cell transistor. At this time, the cell plate terminal remains still at the half voltage Vcc/2.
When a sense amplifier is operated, the voltage on the bit line and storage node is changed to the supply voltage Vcc or the ground voltage Gnd, and the cell plate terminal remains still at the half voltage Vcc/2. As a result, in the conventional stressing method, a voltage across a storage capacitor is not more than the half voltage Vcc/2 even though the supply voltage Vcc is raised. Also, the word line must be disabled after being enabled for the stress test operation. In this connection, to stress all cells in the chip, the word line enable/disable operations must be repeated with complexity and inefficiency. Further, in the case where the stress operation is performed with respect to 10 to 100 word lines at a time, a high voltage must be applied to drive the word lines. However, the application of such a high voltage results in a severe damage in cell transistors and storage capacitors. For this reason, it is impossible to make the word line drive voltage high. To the contrary, in the case where a low voltage is applied to drive the word lines, it is impossible to perform the stress test operation through the word lines.
As mentioned above, in the conventional stress test method, much time is required in performing the stress test operation with respect to all the cells in the chip. Also, because the voltage across the storage capacitor has such a small value of Vcc/2 at most, a long stress time is required in removing a fault in the storage capacitor. Further, there is a limitation in increasing the voltage across the storage capacitor.